2.3 Application Processor Subsystem (APSS)

The APSS hosts up to two Arm Cortex-A32 cores outfitted with an ample amount of cache. Each Cortex-A32 core has a 32KB instruction and a 32KB data Level 1 cache. Both cores share 512KB of Level 2 cache with a built-in cache coherency controller. The cache size is chosen to maximize processor performance, given that the system memory blocks have different and limited bandwidth. This approach enables balance between performance and energy efficiency.

The APSS is optimized for running Linux-based embedded applications that can benefit from the power efficiency and high-performance of the Cortex-A32 cores (see Figure 2-3).

Figure 2-3 Application Processor Subsystem Architecture for E7 Devices

The APSS includes an interrupt controller that handles interrupt requests from local and shared peripherals. The local peripherals include MHU that enables IPC to the SESS and to the other subsystems.

The Cortex-A32 cores include a full-featured Memory Management Unit (MMU), enabling execution of a Linux® operating system. The Linux kernel can be configured with Symmetric Multiprocessing (SMP) support, making most of the dual-core performance capabilities.

Alternatively, the Cortex-A32 cores can be utilized by several SMP-capable Real-Time Operating Systems (RTOS), such as Azure RTOS (formerly ThreadX).